
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:12:05 12/16/2008
-- Design Name:   VGA_contoller
-- Module Name:   E:/projects/ISE 9.2/VGA_interface/vga_tb.vhd
-- Project Name:  VGA_interface
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: VGA_contoller
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY vga_tb_vhd IS
END vga_tb_vhd;

ARCHITECTURE behavior OF vga_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT VGA_contoller
	PORT(
		clk : IN std_logic;
		reset : IN std_logic;
		PB_DOWN : IN std_logic;
		PB_UP : IN std_logic;
		PB_LEFT : IN std_logic;
		PB_RIGHT : IN std_logic;
		SW_0 : IN std_logic;
		SW_1 : IN std_logic;
		SW_2 : IN std_logic;
		SW_3 : IN std_logic;          
		VGA_OUT_RED : OUT std_logic_vector(7 downto 0);
		VGA_OUT_GREEN : OUT std_logic_vector(7 downto 0);
		VGA_OUT_BLUE : OUT std_logic_vector(7 downto 0);
		VGA_OUT_PIXEL_CLOCK : OUT std_logic;
		VGA_COMP_SYNCH : OUT std_logic;
		VGA_OUT_BLANK_Z : OUT std_logic;
		VGA_HSYNCH : OUT std_logic;
		VGA_VSYNCH : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL PB_DOWN :  std_logic := '0';
	SIGNAL PB_UP :  std_logic := '0';
	SIGNAL PB_LEFT :  std_logic := '0';
	SIGNAL PB_RIGHT :  std_logic := '0';
	SIGNAL SW_0 :  std_logic := '0';
	SIGNAL SW_1 :  std_logic := '0';
	SIGNAL SW_2 :  std_logic := '0';
	SIGNAL SW_3 :  std_logic := '0';

	--Outputs
	SIGNAL VGA_OUT_RED :  std_logic_vector(7 downto 0);
	SIGNAL VGA_OUT_GREEN :  std_logic_vector(7 downto 0);
	SIGNAL VGA_OUT_BLUE :  std_logic_vector(7 downto 0);
	SIGNAL VGA_OUT_PIXEL_CLOCK :  std_logic;
	SIGNAL VGA_COMP_SYNCH :  std_logic;
	SIGNAL VGA_OUT_BLANK_Z :  std_logic;
	SIGNAL VGA_HSYNCH :  std_logic;
	SIGNAL VGA_VSYNCH :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: VGA_contoller PORT MAP(
		clk => clk,
		reset => reset,
		PB_DOWN => PB_DOWN,
		PB_UP => PB_UP,
		PB_LEFT => PB_LEFT,
		PB_RIGHT => PB_RIGHT,
		SW_0 => SW_0,
		SW_1 => SW_1,
		SW_2 => SW_2,
		SW_3 => SW_3,
		VGA_OUT_RED => VGA_OUT_RED,
		VGA_OUT_GREEN => VGA_OUT_GREEN,
		VGA_OUT_BLUE => VGA_OUT_BLUE,
		VGA_OUT_PIXEL_CLOCK => VGA_OUT_PIXEL_CLOCK,
		VGA_COMP_SYNCH => VGA_COMP_SYNCH,
		VGA_OUT_BLANK_Z => VGA_OUT_BLANK_Z,
		VGA_HSYNCH => VGA_HSYNCH,
		VGA_VSYNCH => VGA_VSYNCH
	);

	clocking: process
	begin
		clk <= '0';
		wait for 5 ns;
		clk <= '1';
		wait for 5 ns;
	end process;
	
	reset_p: process
	begin
		reset <= '0';
		wait for 50 ns;
		reset <= '1';
		wait;
	end process;

	PB_DOWN <= '1';
	PB_UP <= '1';
	PB_LEFT <= '1';
	PB_RIGHT <= '1';
	SW_0 <= '1';
	SW_1 <= '1';
	SW_2 <= '1';
	SW_3 <= '1';
END;
